Abstract: Viterbi Decoder employed in digital wireless communication plays a dominant role in overall power consumption of trellis coded modulation (TCM) decoder. Using T-algorithm dramatically reduces the decoding speed .The key point in improving clock speed of T-algorithm is to quickly find the optimal Path Metric (PMoptimal). The proposed Viterbi Decoder (VD) implementation can reduce the power consumption with less reduction in the maximum decoding speed. The trellis path in the circuit is found using trellis coded modulation. Pre-computation technique has been adopted for the trellis coded modulation. This paper focuses on the realization of convolutional encoder and Viterbi decoder with a constraint length (K) of 7 and code rate (k/n) of 3/4 using Field Programmable gate array (FPGA) Technology. The convolutional encoder and Viterbi decoder (VD) using T-algorithm has been coded in Verilog HDL code and implemented in Xilinx ISE 14.2